|
||||||||||
| PREV CLASS NEXT CLASS | FRAMES NO FRAMES | |||||||||
| SUMMARY: NESTED | FIELD | CONSTR | METHOD | DETAIL: FIELD | CONSTR | METHOD | |||||||||
java.lang.Objectcom.newisys.dv.DVSimulation
public final class DVSimulation
Provides access to events and structures in the current simulation.
This class is the user code's central access point to the simulation. Methods provide:
| Constructor Summary | |
|---|---|
DVSimulation(com.newisys.verilog.VerilogSimulation verilogSim,
SimulationManager simManager,
OVAEngine ovaEngine)
Create a new DVSimulation with the given VerilogSimulation and SimulationManager. |
|
| Method Summary | ||
|---|---|---|
void |
callVerilogTask(String name,
Object... args)
Execute the given HDL task. |
|
|
createMailbox()
Creates a new mailbox. |
|
Semaphore |
createSemaphore(int permits)
Creates a new semaphore with the specified number of permits. |
|
SimulationThread |
currentThread()
Returns the current SimulationThread. |
|
void |
delay(long ticks)
Block the current thread for the specified number of simulation ticks. |
|
void |
finish()
Ends the current simulation. |
|
SimulationThread[] |
fork(Runnable... rs)
Starts a set of new simulation threads with generated names. |
|
SimulationThread |
fork(Runnable r)
Starts a new simulation thread with a generated name. |
|
SimulationThread |
fork(String name,
Runnable r)
Starts a new simulation thread with the given name. |
|
List<String> |
getArguments()
Returns the arguments passed to this simulation. |
|
ClockSignal |
getClockSignal(String name,
int depth)
Returns a ClockSignal object for the specified signal. |
|
InOutSignal |
getConcatInOutSignal(InOutSignal... signals)
Returns an InOutSignal that is the concatenation of multiple signals. |
|
InputSignal |
getConcatInputSignal(InputSignal... signals)
Returns an InputSignal that is the concatenation of multiple signals. |
|
OutputSignal |
getConcatOutputSignal(OutputSignal... signals)
Returns an OutputSignal that is the concatenation of multiple signals. |
|
ClockSignal |
getDefaultClockSignal()
Returns the default ClockSignal object for the simulation. |
|
InOutSignal |
getInOutSignal(String name,
ClockSignal clock,
com.newisys.verilog.EdgeSet inputEdges,
int inputSkew,
com.newisys.verilog.EdgeSet outputEdges,
int outputSkew,
int depth)
Returns an InOutSignal object for the specified signal. |
|
InputSignal |
getInputSignal(String name,
ClockSignal clock,
com.newisys.verilog.EdgeSet inputEdges,
int inputSkew,
int depth)
Returns an InputSignal object for the specified signal. |
|
com.newisys.verilog.VerilogObject |
getObjectByName(String name)
Looks up an HDL object by name. |
|
OutputSignal |
getOutputSignal(String name,
ClockSignal clock,
com.newisys.verilog.EdgeSet outputEdges,
int outputSkew)
Returns an OutputSignal object for the specified signal. |
|
OVAEngine |
getOVAEngine()
Get the OVAEngine for this DVSimulation. |
|
InOutSignal |
getPartialInOutSignal(InOutSignal baseSignal,
int highBit,
int lowBit)
Returns an InOutSignal based on a bit range of another signal. |
|
InputSignal |
getPartialInputSignal(InputSignal baseSignal,
int highBit,
int lowBit)
Returns an InputSignal based on a bit range of another signal. |
|
OutputSignal |
getPartialOutputSignal(OutputSignal baseSignal,
int highBit,
int lowBit)
Returns an OutputSignal based on a bit range of another signal. |
|
PRNG |
getRandom()
Returns the random number generator associated with the current thread. |
|
PRNGFactory |
getRandomFactory()
Returns the random number generator factory associated with the current thread. |
|
long |
getSimTime()
Returns the current simulation time. |
|
boolean |
hasOVASupport()
Returns whether or not OVA is supported in this DVSimulation. |
|
void |
join(SimulationThread thread)
Waits for the specified thread to complete. |
|
void |
joinAll(SimulationThread... threads)
Waits for all specified threads to complete. |
|
void |
joinAny(SimulationThread... threads)
Waits for any of the specified threads to complete. |
|
void |
joinChildren()
Waits for all child threads of this thread to complete. |
|
void |
notifyOf(Event e)
Notify the simulation that the specified event has occured. |
|
void |
registerJavaTask(Method method,
Object object)
Registers the given method as callable from the HDL. |
|
void |
registerJavaTasks(Class cls)
Registers all static methods in the given class (and any superclasses) whose names start with "task_" as callable from the HDL. |
|
void |
registerJavaTasks(Object object)
Registers all methods in the class of the given object (and any superclasses) whose names start with "task_" as callable from the HDL. |
|
void |
setRandom(PRNG random)
Sets the random number generator associated with the current thread. |
|
void |
setRandomFactory(PRNGFactory randomFactory)
Sets the random number generator factory associated with the current thread. |
|
void |
stop()
Stops the current simulation. |
|
void |
terminate()
Terminates this thread and all of its child threads. |
|
void |
terminateAll()
Terminates all threads in the current simulation. |
|
void |
waitFor(Event e)
Waits for the specified event to occur. |
|
void |
waitForAll(Collection<? extends Event> events)
Waits for all of the specified events to occur. |
|
void |
waitForAll(Event... events)
Waits for all of the specified events to occur. |
|
void |
waitForAny(Collection<? extends Event> events)
Waits for any of the specified events to occur. |
|
void |
waitForAny(Event... events)
Waits for any of the specified events to occur. |
|
void |
waitForSimTime(long simTime)
Block the current thread until the specified simulation time. |
|
void |
yield()
Yields execution to another thread. |
|
| Methods inherited from class java.lang.Object |
|---|
equals, getClass, hashCode, notify, notifyAll, toString, wait, wait, wait |
| Constructor Detail |
|---|
public DVSimulation(com.newisys.verilog.VerilogSimulation verilogSim,
SimulationManager simManager,
OVAEngine ovaEngine)
verilogSim - the VerilogSimulation to be used by this DVSimulationsimManager - the SimulationManager to be used by this DVSimulationovaEngine - the OVAEngine to be used by this DVSimulation| Method Detail |
|---|
public void registerJavaTasks(Class cls)
cls - the class to register static methods frompublic void registerJavaTasks(Object object)
object - the object to register methods from
public void registerJavaTask(Method method,
Object object)
method - the method to registerobject - the object to invoke the method on
public void callVerilogTask(String name,
Object... args)
name - the name of the HDL taskargs - an array of arguments to pass to the verilog taskpublic <T> Mailbox<T> createMailbox()
T - the type of objects contained by the mailbox
public Semaphore createSemaphore(int permits)
permits - the initial number of permits in the semaphore
public SimulationThread currentThread()
public SimulationThread fork(String name,
Runnable r)
name - the name of this thread, for debugging purposesr - the code to run for this thread
public SimulationThread fork(Runnable r)
r - the code to run for this thread
public SimulationThread[] fork(Runnable... rs)
rs - the code to run for each thread
public void join(SimulationThread thread)
thread - the thread to wait forpublic void joinAll(SimulationThread... threads)
threads - an array of SimulationThreads to wait forpublic void joinAny(SimulationThread... threads)
threads - an array of SimulationThreads to wait forpublic void joinChildren()
public void yield()
public void terminate()
public void terminateAll()
public void stop()
public void finish()
public void notifyOf(Event e)
e - the event that has occurredpublic void waitFor(Event e)
e - the event to wait forpublic void waitForAll(Event... events)
events - an array of events to wait forpublic void waitForAll(Collection<? extends Event> events)
events - a collection of events to wait forpublic void waitForAny(Event... events)
events - an array of events to wait forpublic final void waitForAny(Collection<? extends Event> events)
events - a collection of events to wait forpublic PRNG getRandom()
public void setRandom(PRNG random)
random - the random number generator to associate with the current
threadpublic PRNGFactory getRandomFactory()
public void setRandomFactory(PRNGFactory randomFactory)
randomFactory - the random number generator factory to associate
with the current threadpublic List<String> getArguments()
public long getSimTime()
public com.newisys.verilog.VerilogObject getObjectByName(String name)
name - the name of the HDL object
public ClockSignal getClockSignal(String name,
int depth)
name - the name of the signaldepth - the desired back-reference depth
public ClockSignal getDefaultClockSignal()
public InputSignal getInputSignal(String name,
ClockSignal clock,
com.newisys.verilog.EdgeSet inputEdges,
int inputSkew,
int depth)
name - the name of the signalclock - the ClockSignal used to sample this signalinputEdges - the clock edges to sample this signal oninputSkew - the input skew in ticks (should be negative)depth - the desired back-reference depth
public InputSignal getPartialInputSignal(InputSignal baseSignal,
int highBit,
int lowBit)
highBit - lowBit + 1.
baseSignal - the InputSignal containing the bits from which the new
InputSignal will be createdhighBit - the bit of baseSignal that will become the
MSB of the new InputSignallowBit - the bit of baseSignal that will become the
LSB of the new InputSignal
public InputSignal getConcatInputSignal(InputSignal... signals)
signals - an array of InputSignals to concatenate
public OutputSignal getOutputSignal(String name,
ClockSignal clock,
com.newisys.verilog.EdgeSet outputEdges,
int outputSkew)
name - the name of the signalclock - the ClockSignal used to drive this signaloutputEdges - the clock edges to drive this signal onoutputSkew - the output skew in ticks (should be positive)
public OutputSignal getPartialOutputSignal(OutputSignal baseSignal,
int highBit,
int lowBit)
highBit - lowBit + 1.
baseSignal - the OutputSignal containing the bits from which the new
OutputSignal will be createdhighBit - the bit of baseSignal that will become the
MSB of the new OutputSignallowBit - the bit of baseSignal that will become the
LSB of the new OutputSignal
public OutputSignal getConcatOutputSignal(OutputSignal... signals)
signals - an array of OutputSignals to concatenate
public InOutSignal getInOutSignal(String name,
ClockSignal clock,
com.newisys.verilog.EdgeSet inputEdges,
int inputSkew,
com.newisys.verilog.EdgeSet outputEdges,
int outputSkew,
int depth)
name - the name of the signalclock - the ClockSignal used to sample and drive this signalinputEdges - the clock edges to sample this signal oninputSkew - the input skew in ticks (should be negative)outputEdges - the clock edges to drive this signal onoutputSkew - the output skew in ticks (should be positive)depth - the desired back-reference depth
public InOutSignal getPartialInOutSignal(InOutSignal baseSignal,
int highBit,
int lowBit)
highBit - lowBit + 1.
baseSignal - the InOutSignal containing the bits from which the new
InOutSignal will be createdhighBit - the bit of baseSignal that will become the
MSB of the new InOutSignallowBit - the bit of baseSignal that will become the
LSB of the new InOutSignal
public InOutSignal getConcatInOutSignal(InOutSignal... signals)
signals - an array of InOutSignals to concatenate
public void waitForSimTime(long simTime)
simTime - the simulation time at which to unblock the current threadpublic void delay(long ticks)
ticks - the number of ticks to wait before unblocking the threadpublic OVAEngine getOVAEngine()
DVRuntimeException is thrown.
DVRuntimeException - if no OVA support is available.public boolean hasOVASupport()
true if OVA is supported in this simulation,
false otherwise
|
||||||||||
| PREV CLASS NEXT CLASS | FRAMES NO FRAMES | |||||||||
| SUMMARY: NESTED | FIELD | CONSTR | METHOD | DETAIL: FIELD | CONSTR | METHOD | |||||||||