Copyright © 2005 Newisys, Inc. Licensed under the Open Software License version 2.0.
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Last updated 10/19/05
The purpose of this document is to describe how to run the sample programs provided with Jove as quickly as possible. For more in-depth Jove information, please refer to the Jove user documentation.
To run the any of samples, you will need the following software installed:
Additionally, the Verilog/non-behavioral samples (and3, and3param) require:
jove-dist-1.0/
bin/
docs/
native/
samples/
tutorial/
To run the sample programs, you will need to have the JAVA_HOME environment variable set to the root of your Java installation (i.e. ${JAVA_HOME}/bin/java should exist). To run the and3 and and3param examples, you will also need to set the appropriate environment variable for your simulator. If you're using VCS, set the VCS_HOME environment variable to the root of your VCS installation (i.e. ${VCS_HOME}/bin/vcs should exist). If you're using cver, set the CVER_HOME environment variable to the root of your cver installation (i.e. ${CVER_HOME}/bin/cver should exist). You will also need to have the Java, GNU Make, and GCC binary directories in your path.
A behavioral example is provided to show how Jove can be used to create behavioral models. The code for this example can be found in jove-dist-1.0/samples/src/com/newisys/samples/behavioral. The example itself merely forks two threads: one that places integers into a mailbox, and one that consumes integers from the mailbox.
To run the behavioral example, you do not need a Verilog simulator installed. The following commands should run the example.
cd jove-dist-1.0/samples
make behavioral
The 'and3' example is provided to show how to connect Jove to a Verilog simulator. The code for this example can be found in jove-dist-1.0/samples/src/com/newisys/samples/and3. In this example, the DUT being simulated is a simple 3-input AND gate. The testbench exhaustively tests the DUT, then generates constrained random stimulus.
To run the 'and3' example, you need a copy of VCS or cver. The following commands run the example using VCS. Substitute "cver" for "vcs" to run the example with the cver simulator.
cd jove-dist-1.0/samples
make SIMULATOR=vcs and3
The 'and3param' example is identical to the 'and3' example except that the 'and3' Verilog module is instantiated twice in the top-level Verilog file. The parameterization features of the ifgen tool are used to allow the testbench to access signals in both DUTs with a minimum of change to the ifgen specification. The code for this example can be found in jove-dist-1.0/samples/src/com/newisys/samples/and3param. The testbench exhaustively tests the DUTs, then generates constrained random stimulus.
To run the 'and3param' example, you need a copy of VCS or cver. The following commands run the example using cver. Substitute "vcs" for "cver" to run the example with the VCS simulator.
cd jove-dist-1.0/samples
make SIMULATOR=cver and3param